This invention relates to a device for connecting 8-bit and 16-bit modules to a 16-bit microprocessor system, that finds application in 16-bit microprocessor systems and computers.
There is known a device for connecting a 16-bit microprocessor system to 8-bit modules, which device contains a 16-bit microprocessor system having its primary data inputs and outputs coupled to half of the information inputs and outputs of a primary bidirectional data buffer, while its secondary inputs and outputs are coupled with half of the information inputs and outputs of a secondary bidirectional data buffer. The address outputs of the 16-bit microprocessor system are connected to the information inputs of a unidirectional address buffer having its outputs connected to the address inputs of the 8-bit modules, the information inputs and outputs of the 8-bit modules being connected to the other half of the information inputs and outputs of the primary bidirectional data buffer and the bidirectional switching data buffer. The 16-bit microprocessor primary inputs and outputs are connected to the information outputs of a buffer register, having its information inputs, in turn, coupled with half of the information inputs and outputs of the primary bidirectional data buffer. The output controlling the twin cycle of the 16-bit microprocessor system is connected to the homonymic input of the control circuit, which includes an output for setting wait periods connected to the homonymic input of the 16-bit microprocessor system. The outputs of the control circuit that control the data buffers are connected to the control inputs of the primary bidirectional data buffer, the buffer register, the bidirectional switching data buffer and the secondary bidirectional data buffer. The address modification control output of the control circuit is connected to the control input of an address modification circuit, its address input being, in turn, coupled to the address outputs of the 16-bit microprocessor system, while its address output is connected to the information inputs of the unidirectional address buffer, the outputs of which are connected to the address input of the control circuit, having a control output connected to the control input of the unidirectional address buffer, and a control input for setting additional wait periods is coupled to the homonymic output of the 8-bit modules.
The control circuit includes a unit controlling the twin cycle, the outputs of which are connected to a unit that sets wait periods, a unit controlling the data buffers, and a unit controlling the address buffers.
The unit controlling the twin cycle follows and decodes the type of the transfer operation executed from the 16-bit microprocessor system. The unit for setting wait periods, the unit controlling the address circuits and the address modification circuit are not activated at byte exchange operations. The address fed to the address outputs of the 16-bit microprocessor system is transferred through the unidirectional address buffer to the address inputs of the 8-bit modules unchanged. If the address is even, the primary data inputs and outputs of the 16-bit microprocessor system are coupled to the information inputs and outputs of the 8-bit modules by means of the primary bidirectional data buffer. At an odd address, the information inputs and outputs of the 8-bit modules are coupled to the secondary data inputs and outputs of the 16-bit microprocessor system by means of the bidirectional switching data buffer. At operations with word (two byte) exchange, the unit controlling the twin cycle activates the unit for setting wait periods and the latter places the 16-bit microprocessor system in a "wait" state. This state extends the operation for as many clock periods as are necessary for execution of additional byte exchange cycle. At the same time, the conditions for setting additional wait periods are followed. These conditions are required by the 8-bit modules to accomplish a single cycle of byte exchange. The unit controlling the twin cycle performs its duties by the use of the unit that controls the data buffers, and the unit controlling the address circuits.
During the first cycle, the address from the address outputs of the 16-bit microprocessor system is transferred unchanged through the unidirectional address buffer to the address inputs of the 8-bit modules. At write instructions, the unit controlling the data buffers controls the transfer of the byte placed on the primary data outputs of the 16-bit microprocessor system, to the information inputs of the 8-bit modules. The byte transfer is accomplished through the primary bidirectional data buffer. At read operations, the unit controlling the data buffers provides the storing of the byte that is on the information outputs of the 8-bit modules. The byte is stored in the buffer register after passing through the primary bidirectional data buffer.
The second exchange cycle is completely controlled by the unit controlling the twin cycle. At this cycle, address modification is accomplished in the address modification circuit. This provides selection and handling of the second byte of the word. The modified address is fed through the unidirectional address buffer to the address inputs of the 8-bit modules. During write operations, the unit controlling the data buffers provides the transfer of the byte, from the secondary data outputs of the 16-bit microprocessor system, to the information inputs of the 8-bit modules. The transfer of the byte is accomplished through the bidirectional switching data buffer.
During read operations, the unit controlling the data buffers provides the transfer of a byte from the information outputs of the 8-bit modules, through the bidirectional switching data buffer, to the secondary data inputs of the 16-bit microprocessor system. At the same time, the buffer register moves the data byte, stored in it during the first exchange cycle, to the primary data inputs of the 16-bit microprocessor system. With respect to the 8-bit modules, the information exchange with the 16-bit microprocessor system is accomplished in bytes regardless of the type of the executed operation. The latter may require byte exchange or word exchange.
Disadvantages of the described device are the linear address allocation and the means for word exchange between the 16-bit microprocessor system and only part of the 8-bit modules. Only operations with byte exchange and nonlinear allocation of the addresses are allowed to the other 8-bit modules. These restrictions are imposed by the 16-bit microprocessor system. Another disadvantage of the device is the low rate of word exchange between the 16-bit microprocessor system and the 16-bit modules.